This course bridges the gap between the basic technical information in a product brief and the detailed data in a comprehensive hardware manual.
(35 mins) Released: 12/28/2009 Updated: 04/01/2010

This course begins the introduction of the SH 2 CPU core. The course provides an overview of the core, programmers model, load-store architecture, new instructions, features of the instruction set, and closes with subroutine calls.
(25 mins) Released: 12/28/2009 Updated: 04/01/2010

This course continues the introduction into the SH2 core. This course introduces CPU error detection, pipeline and flow control, and closes with SH2 programming tips.
(25 mins) Released: 12/28/2009 Updated: 04/01/2010

This course begins the introduction of the SH2A CPU core. This course provides an overview of the core, programmers model, load-store architecture, new instructions, features of the instruction set, and closes with subroutine calls.

(25 mins) Released: 04/09/2010 Updated: 04/09/2010

This course continues the introduction into the SH2A core. This course introduces the Floating Point Unit, CPU error detection, pipeline and flow control, and closes with SH2A programming hints.
(30 mins) Released: 12/28/2009 Updated: 04/01/2010

This course continues the introduction into the SH2A core. This course introduces the Floating Point Unit Register Banks, on-chip Cache (including Cache read hits/misses), and closes with ten helpful programming tips.
(20 mins) Released: 12/28/2009 Updated: 04/01/2010

This course shows the basic multi-function timer pulse unit (MTU) and its latest versions: the MTU2 and MTU2S found on newer members of the SH-2 and SH-2A families.
(35 mins) Released: 12/28/2009 Updated: 04/01/2010

This course provides an overview of the direct memory access controller and the interrupt transfer controller on the SH-2 and SH-2A families of 32-bit RISC microcontrollers, which are members of the SuperH® series.
(40 mins) Released: 12/28/2009 Updated: 04/01/2010

SH7216 RCAN-ET Peripherals and CAN API
(30 mins) Released: 04/23/2010 Updated: 04/23/2010

This course details the SH7216 Ethernet module and its operation.
(30 mins) Released: 04/23/2010 Updated: 04/23/2010

This course provides an overview of the bus state controller and the data transfer controller on SH-2 and SH-2A families of 32-bit RISC microcontrollers, members of the SuperH® series.
(40 mins) Released: 12/28/2009 Updated: 04/01/2010

This course bridges the gap between the basic technical information in a product brief and the detailed data in a comprehensive hardware manual.
(40 mins) Released: 12/28/2009 Updated: 04/01/2010